Highly-Integrated Integrated Circuit (IC) devices such as a System-On-a-Chip (SoC) are widely used. Wireless systems using a SoC may have fairly complex clocking requirements. For example, a clock synthesizer may be required to generate clocks from 285 MHz up to 2.4 GHz due to the various communication protocols and bands used. However, a single voltage-controlled oscillator (VCO) has a much more limited output frequency range.
FIG. 1 shows a clock synthesizer using a divider to generate a wide range of output frequencies. A reference clock is applied to Phase-Locked Loop (PLL) 102, which generates an internal clock having a frequency range of 1.4 to 2.9 GHz. Dividers 104 then divide this clock by various selectable divisors, such as 1, 2, 3, 4, 6, 8. One or more of the outputs of dividers 104 can be output from synthesizer 100 for use by the system.
The range of output frequencies generated by dividers 104 is from 175 MHz up to 2.9 GHz. For example, when a 500 MHz clock is desired, dividers 104 can be set to a divisor of 3, which has a range of 476 MHz to 967 MHz, or to a divisor of 4, which has a range of 350 MHz to 725 MHz. PLL 102 can be adjusted to generate a PLL output of 1.5 GHz, when a divisor of 3 is selected for dividers 104, or a PLL output of 2.0 GHz when a divisor of 4 is selected for dividers 104. The PLL clock output from PLL 102 can be adjusted by adjusting the feedback divider in PLL 102.
Some simple communications systems require only an in-phase clock, where the clock and its inverse are used. The inverse clock is 180 degrees out of phase from the clock.
More complex communications systems may require a quadrature clock. A quadrature clock has the clock and inverse clock that are 180 degrees out of phase, and also has a pair of clocks that are 90 degrees out of phase with the clock and inverse clock.
FIG. 2 highlights a quadrature input clock and a divided-down quadrature output clock. An input clock IN has four phased clocks that are separated from each other by 90-degree increments. The four clocks include a true in-phase clock IN-IP, a complement in-phase clock IN-IN that has a 180 degree phase delay from IN-IP, a true quadrature phase clock IN-QP that has a 90 degree phase delay from IN-IP, and a complement quadrature phase clock IN-QN, that has a 270-degree phase delay from IN-IP. These are quadrature or IQ signals.
When a divisor of 3 is selected for dividers 104, then the output clock has a period that is three times the period of the input clock. The same 90-degree phase spacings are desired for the divided-by-3 output clocks. OUT-IP, OUT-QP, OUT-IN, and OUT-QN are generated at 90-degree phase increments, with phase delays of 0, 90, 180, and 270, respectively. Ideally, the duty cycle is 50% for all input and output clock waveforms.
Clock dividers with even divisors are typically easier to implement than are odd-divisor clock dividers. For example, divisors of 2, 4, 6, and 8 are typically easier to implement in dividers 104 that the odd divisor of 3.
Various prior-art approaches have been used to generate clocks. Analog approaches often have high power consumption and require a large area. Analog approaches may not be feasible for low-voltage power supplies. Digital dividers may require calibration. Some approaches do not provide a 50% duty cycle.
Some prior-art approaches simply use delay lines to generate the phased clocks. However, clock accuracy may be poor, especially when quadrature clocks are needed. The clock range may be limited. When inductors are used, a large chip area and cost may result. Analog devices typically do not scale down to smaller process geometries as do digital circuits.
What is desired is a clock divider with an odd divisor. A divide-by-3 circuit is desired that generates clocks with 50% duty cycles. A digital circuit that divides a quadrature clock by an odd divisor to generate a quadrature output clock with good phase accuracy is desirable.